1. Field of the Invention
The present invention generally relates to a semiconductor memory device. More specifically, the present invention is directed to a double data rate type synchronous dynamic random access memory (DDR type SDRAM, or DDP-SDRAM) capable of securing a large latch margin.
2. Description of the Related Art
While central processing units (CPUs) are operable in high speeds, SDRAMs operable in synchronism with clock signals are used in main storage units of computers. To further increase operating speeds, 2-bit prefetch type SDRAMs have been recently proposed. In a 2-bit prefetch type SDRAM, 2-bit data are read/written at the same time.
First, a first prior art semiconductor memory device constituted by a 2-bit prefetch type SDRAM will be described.
FIG. 36 and FIG. 37 are schematic block diagrams for representing an electric circuit arrangement of a semiconductor memory device according to the first prior art. FIG. 38 is a timing chart for explaining operations of this first prior art semiconductor memory device.
As schematically shown in FIG. 36 and FIG. 37, this first prior art semiconductor memory device is mainly arranged by a clock signal circuit 201, and a data-in circuit 202.
Precisely speaking, as shown in FIG. 36, the clock signal circuit 201 contains an input buffer 2011, a rise transition pulse generating circuit 2012, a delay circuit 2013, a frequency dividing circuit 2014, and a rise transition pulse generating circuit 2015.
As shown in FIG. 37(a), the data-in circuit 202 contains an input buffer 2021, register circuits 2022, 2023, 2024, 2025, and also a data bus drive circuit 2026.
Next, a description will be made of operations of the first prior art semiconductor memory device constituted by the 2-bit prefetch type SDRAM with reference to FIG. 37 to FIG. 38.
In the clock signal circuit 201 shown in FIG. 36, the rise transition pulse generating circuit 2012 detects a rise edge of a clock signal CLK which is externally entered via an input buffer 2011 to thereby an one-shot pulse signal ".PHI.clk". The frequency dividing circuit 2014 frequency-divides an input clock signal by a 1/2 frequency, which is produced by delaying the entered clock signal CLK by preselected time via the delay circuit 2013. The rise transition pulse generating circuit 1015 detects a rise edge of the frequency-divided clock signal derived from the frequency dividing circuit 2014 to thereby generate another one-shot pulse signal ".PHI.clkdin". This one-shot pulse signal ".PHI.clkdin" owns a time period two times higher than that of the clock signal CLK.
In the data-in circuit 202 shown in FIG. 37(a), a data input signal DINi (i=1 to 8) indicates 1-bit data among 8-bit parallel input data. The register circuit 2022 acquires the data input signal DINi derived via the input buffer 2021 in response to the one-shot pulse ".PHI.clk" produced by the rise transition of the clock signal CLK. The register circuit 2023 acquires the signal saved from the register circuit 2022 in response to the next one-shot pulse signal ".PHI.clk". Next, the register circuit 2024 and the register circuit 2025 acquire at the same time both the data saved in the register circuits 2022 and 2023 in response to the one-shot pulse signal ".PHI.clkdin" produced every time the two cycles of the clock signal CLK have passed. At this stage, in order to avoid the mis-latch operation, this one-shot pulse signal ".PHI.clkdin" is delayed by the delay circuit 2013 so as to be supplied after the one-shot pulse signal ".PHI.clk". The data bus drive circuit 2026 supplies both the output data "ed" derived from the register circuit 2024 and the output data "od" derived from the register circuit 2025 in a parallel manner to even-numbered data buses DBEi (i=1 to 8) and also odd-numbered data buses DBOi (i=1 to 8), so that the input data may be written into a memory cell (not shown).
It should be understood in this first prior art memory circuit that all of these register circuits 2022, 2023, 2024, and 2025 shown in FIG. 37(a) own the same circuit arrangements as a circuit arrangement of a register circuit 203 shown in FIG. 37(b). This register circuit 203 owns an inverter I1, gates G1, G2, and latches L1, L2. In response to a fall edge of an external clock signal ".PHI.", the input data IN is latched by the latch circuit L1 by opening the gate G1, and also the data latched by this latch circuit L1 is latched by another latch circuit L2 by opening the gate G2 in response to a rising edge of this external clock signal ".PHI.". As a result, 1-bit data is held in this register circuit 203 during 1 time period of the external clock signal ".PHI.".
Next, a description of a second prior art semiconductor memory device will be explained, which is arranged by a 2-bit prefetch type SDRAM. FIG. 39 and FIG. 40 are schematic block diagrams for showing an electric circuit arrangement of a semiconductor memory device according to the second prior art invention. FIG. 41 is a timing chart for explaining operation of this second prior art memory device.
This semiconductor memory device of the second prior art is mainly arranged by a clock signal circuit 211, and a data-in circuit 212.
As indicated in FIG. 39, the clock signal circuit 211 contains an input buffer 2111, a frequency dividing circuit 2111, a rise transition pulse generating circuit 2113, a delay circuit 2114, an 1-time-period delay circuit 2115, another frequency dividing circuit 2116, and another rise transition pulse generating circuit 2117.
As indicated in FIG. 40(a), the data-in circuit 212 contains an input buffer 2121, register circuits 2122, 2123, 2124, and 2125, and a data bus drive circuit 2126.
Next, a description will be made of operations of the second prior art semiconductor memory device constituted by the 2-bit prefetch type SDRAM with reference to FIG. 39 to FIG. 41.
In the clock signal circuit 211 shown in FIG. 39, the frequency dividing circuit 2112 frequency-divides an input clock signal by a 1/2 frequency, which is externally entered via the delay circuit 2111. The rise transition pulse generating circuit 2113 detects a rise edge of the frequency-divided clock signal derived from the frequency dividing circuit 2112 to thereby generate an one-shot pulse signal ".PHI.clk". The delay circuit 2114 delays the output signal of the frequency dividing circuit 2112 by preset time. The rise transition pulse generating circuit 2113 detects a rise edge of the output signal derived from the delay circuit 2114 to thereby generate another one-shot pulse ".PHI.clkdin". Also, the 1-time-period delay circuit 2115 delays the output signal of the input buffer 2111 by 1 time period, whereas the frequency dividing circuit 2116 frequency-divides the output signal produced from the 1-time-period delay circuit 2115 by a 1/2 frequency. The rise transition pulse generating circuit 2117 detects a rise edge of the frequency-divided signal of the frequency dividing circuit 2116 to produce another one-shot pulse ".PHI./clk".
In the data-in circuit 212 shown in FIG. 40(a), the register circuit 2112 acquires the data input signal DINi entered via the input buffer 2121 in response to the one-shot pulse signal ".PHI.clk" generated by detecting the rise transition of the frequency-divided clock signal CLK by 2. Also, the register circuit 2123 acquires the output signal derived from the input buffer 2121 in response to the one-shot pulse signal ".PHI./clk" produced by detecting the rise transition of the clock signal CLK which has been delayed by 1 time period and then is frequency-divided by 2. Next, the register circuit 2124 and the register circuit 2125 acquire at the same time both the data saved in the register circuits 2122 and 2123 in response to the one-shot pulse signal ".PHI.clkdin" produced every time the two cycles of the clock signal CLK have passed. At this stage, in order to avoid the mis-latch operation, this one-shot pulse signal ".PHI.clkdin" is delayed so as to be supplied after the one-shot pulse signal ".PHI.clk". The data bus drive circuit 2126 supplies both the output data "ed" derived from the register circuit 2124 and the output data "od" derived from the register circuit 2125 in a parallel manner to even-numbered data buses DBEi (i=1 to 8) and also odd-numbered data buses DBOi (i=1 to 8), so that the input data may be written into a memory cell (not shown).
It should be understood in this second prior art memory device that all of these register circuits 2122, 2123, 2124, and 2125 own the same circuit arrangements as a circuit arrangement of a register circuit 213 shown in FIG. 40(b). This register circuit 213 owns the same arrangement/function as those of the register circuit 203 indicated in FIG. 37(b).
In the above-explained conventional semiconductor memory devices, the operating speed of the clock signal must be necessarily increased so as to increase the data processing speeds. However, since in actual systems with using such an SDRAM, a large number of SDRAMs are mounted on a module board to be driven, there are serious problems in timing skews between the clock signal CLK and the data input signal DINi. As a result, the highspeed operation of the clock signal CLK cannot be readily realized.
The reason why such a timing skew problem occurs is given as follows: That is, the data input signal is acquired only by using the clock signal CLK. To the contrary, very recently, the double data rate type DDR-SDRAM has been proposed, and is now standardized by JEDEC (Joint Electron Device Engineering Council).
In this DDR-SDRAM, the 2-bit prefetch system is employed. The data input signal is acquired by receiving the data strobe signal DS. The time period of the clock signal CLK becomes two times higher than that of the data input signal. This data strobe signal DS is produced together with the data input signal DINi at the same time by a central processing unit (CPU: not shown). The data strobe signal DS and the data input signal DINi are connected to the SDRAM via the wiring lines having the same lengths, so that the timing skew problem between these clock signal CLK and data input signal DINi can be solved. As a consequence, both the problem about the highspeed operation of the clock signal, and the timing skew problem between the clock signal and the data input signal can be solved at the same time. It should be noted that after the data input signal is acquired by using the data strobe signal DS, the acquired data input signal must be converted under control of the clock signal CLK. The control/-converting operations effected at this stage must be firmly carried out, namely a sufficiently large latch margin is required.